The present invention is directed generally to data processing systems, and more particularly, to apparatus for physically and electrically extending a synchronous bus of a processor system.
Many of today's data processing systems incorporate components, in the form of data handling units, interconnected by a bus system for communicating information therebetween. For example, a central processor unit (CPU) may be interconnected by a system bus structure to a memory storage unit, an input/output (I/O) controller which, in turn, may connect to various peripheral devices by an I/O bus. Typically, data communications on such a system bus that are synchronous; that is, signals that implement whatever protocol is used to sequence information transfers arrive at discrete time intervals (hereinafter "bus cycle") established by a system-wide clock signal. Often, also, such information transfers are "handshaken", in the sense that each bus cycle of the transfer is positively acknowledged by a set of control handshake signals provided by at least one, and often times both, units involved in the transfer.
Thanks largely to recent technological advances in the art of semiconductor and integrated circuit fabrication, component operating speeds have significantly increased so that information transfers can be conducted at extremely high speeds or clock rates. For example, the present invention is for use in a processor system having an interconnecting processor system capable of transferring 32-bit data words (plus 4 bits of parity) in bit parallel, word serial fashion at a 25 MHz rate; the bus cycle is 40 ns.
Unfortunately, as operating speeds of such components increase, signal delays exhibited by internal or external semiconductor components (e.g., gates) become less important than those of intercomponent wiring. Efforts are made, therefore, to put as much of the system onto individual integrated chips. Even so, the desire to modify, upgrade, and/or expand existing processor systems will encounter wiring, loading, (i.e., current-handling capability) and other delay problems.
Thus, often it is found necessary or desireable to physically extend the system bus in order to connect additional data (e.g., memory) handling units to the processor system. Unfortunately, wiring delays, and other physical and electrical properties encountered in high speed systems can, and often do, operate to preclude such addition by mere connection to the system bus; rather, additional data handling units are added by coupling them to the system bus through some form of intelligent intervening device that operates to stage or pipeline data transfers between the data handling units connected directly to the system bus and additional data handling units. The fact of staging itself means that signalling from one side of the stage will now be sequenced a minimum of one cycle (and usually more) after their appearance at the other side of the stage. It is, therefore, the job of this intelligent staging device to satisfy the sequencing of each side so that it is transparent to the data handling devices, and does not increase the number of cycles per transaction, other than the necessary stage cycle itself. With high speed data processing systems, this can be an impossible task.